 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Freescale Semiconductor Data Sheet Document Number: MSC8113 Rev. 0, 5/2008 MSC8113 FC-PBGA-431 20 mm x 20 mm Tri-Core Digital Signal Processor * Three StarCoreTM SC140 DSP extended cores, each with an SC140 DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte total), 16 way 16 Kbyte instruction cache (ICache), four-entry write buffer, external cache support, programmable interrupt controller (PIC), local interrupt controller (LIC), and low-power Wait and Stop processing modes. * 475 Kbyte M2 memory for critical data and temporary data buffering. * 4 Kbyte boot ROM. * M2-accessible multi-core MQBus connecting the M2 memory with all three cores, operating at the core frequency, with data bus access of up to 128-bit reads and up to 64-bit writes, central efficient round-robin arbiter for core access to the bus, and atomic operation control of M2 memory access by the cores and the local bus. * Internal PLL configured are reset by configuration signal values. * 60x-compatible system bus with 64 or 32 bit data and 32-bit address bus, support for multi-master designs, four-beat burst transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8 bits controlled by the internal memory controller,.access to external memory or peripherals, access by an external host to internal resources, slave support with direct access to internal resources including M1 and M2 memories, and on-device arbitration for up to four master devices. * Direct slave interface (DSI) using a 32/64-bit slave host interface with 21-25 bit addressing and 32/64-bit data transfers, direct access by an external host to internal and external resources, synchronous or asynchronous accesses with burst capability in synchronous mode, dual or single strobe mode, write and read buffers to improve host bandwidth, byte enable signals for 1/2/4/8-byte write granularity, sliding window mode for access using a reduced number of address pins, chip ID decoding to allow one CS signal to control multiple DSPs, broadcast mode to write to multiple DSPs, and big-endian/little-endian/munged support. * Three mode signal multiplexing: 64-bit DSI and 32-bit system bus, 32-bit DSI and 64-bit system bus, or 32-bit DSI and 32-bit system bus, and Ethernet port (MII/RMII). * Flexible memory controller with three UPMs, a GPCM, a page-mode SDRAM machine, glueless interface to a variety of memories and devices, byte enables for 64- or 32-bit bus widths, * 8 memory banks for external memories, and 2 memory banks for IPBus peripherals and internal memories. Multi-channel DMA controller with 16 time-multiplexed single channels, up to four external peripherals, DONE or DRACK protocol for two external peripherals,.service for up to 16 internal requests from up to 8 internal FIFOs per channel, FIFO generated watermarks and hungry requests, priority-based time-multiplexing between channels using 16 internal priority levels or round-robin time-multiplexing between channels, flexible channel configuration with connection to local bus or system bus, and flyby transfer support that bypasses the FIFO. Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/-law conversion, up to 128 Mbps data rate for all channels, with glueless interface to E1 or T1 framers, and can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97. Ethernet controller with support for 10/100 Mbps MII/RMII/SMII including full- and half-duplex operation, full-duplex flow controls, out-of-sequence transmit queues, programmable maximum frame length including jumbo frames and VLAN tags and priority, retransmission after collision, CRC generation and verification of inbound/outbound packets, address recognition (including exact match, broadcast address, individual hash check, group hash check, and promiscuous mode), pattern matching, insertion with expansion or replacement for transmit frames, VLAN tag insertion, RMON statistics, local bus master DMA for descriptor fetching and buffer access, and optional multiplexing with GPIO (MII/RMII/SMII) or DSI/system bus signals lines (MII/RMII). UART with full-duplex operation up to 6.25 Mbps. Up to 32 general-purpose input/output (GPIO) ports. I2C interface that allows booting from EEPROM devices. Two timer modules, each with sixteen configurable 16-bit timers. Eight programmable hardware semaphores. Global interrupt controller (GIC) with interrupt consolidation and routing to INT_OUT, NMI_OUT, and the cores; twenty-four virtual maskable interrupts (8 per core) and three virtual NMI (one per core) that can be generated by a simple write access. Optional booting external memory, external host, UART, TDM, or I2C. * * * * * * * * * (c) Freescale Semiconductor, Inc., 2008. All rights reserved. Table of Contents 1 2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4 1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.2 Recommended Operating Conditions. . . . . . . . . . . . . .14 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .14 2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .14 2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .38 3.1 Start-up Sequencing Recommendations . . . . . . . . . . .38 3.2 Power Supply Design Considerations. . . . . . . . . . . . . .38 3.3 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .39 3.4 External SDRAM Selection . . . . . . . . . . . . . . . . . . . . . .40 3.5 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . .41 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Figure 9. Internal Tick Spacing for Memory Controller Signals. . . Figure 10.SIU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11.CLKOUT and CLKIN Signals. . . . . . . . . . . . . . . . . . . . . Figure 12.DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13.Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14.Asynchronous Single- and Dual-Strobe Modes Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15.Asynchronous Broadcast Write Timing Diagram . . . . . . Figure 16.DSI Synchronous Mode Signals Timing Diagram . . . . . Figure 17.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 19.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 20.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 21.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 22.MDIO Timing Relationship to MDC . . . . . . . . . . . . . . . . Figure 23.MII Mode Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . Figure 24.RMII Mode Signal Timing . . . . . . . . . . . . . . . . . . . . . . . Figure 25.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . Figure 26.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 27.EE Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 28.Test Clock Input Timing Diagram. . . . . . . . . . . . . . . . . . Figure 29.Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . . . Figure 30.Test Access Port Timing Diagram . . . . . . . . . . . . . . . . . Figure 31.TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 32.Core Power Supply Decoupling. . . . . . . . . . . . . . . . . . . Figure 33.VCCSYN Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 34.MSC8113 Mechanical Information, 431-pin FC-PBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 24 25 26 27 28 28 30 31 31 32 32 33 33 34 34 35 35 36 37 37 37 37 38 39 42 3 4 5 6 7 List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. MSC8113 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 StarCore(R) SC140 DSP Extended Core Block Diagram . 3 MSC8113 Package, Top View. . . . . . . . . . . . . . . . . . . . . 5 MSC8113 Package, Bottom View . . . . . . . . . . . . . . . . . . 6 Overshoot/Undershoot Voltage for VIH and VIL. . . . . . . 15 Start-Up Sequence: VDD and VDDH Raised Together . . 16 Start-Up Sequence: VDD Raised Before VDDH with CLKIN Started with VDDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Timing Diagram for a Reset Configuration Write . . . . . 20 MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 2 Freescale Semiconductor SC140 Extended Core MQBus Boot ROM 128 SC140 Extended Core SC140 Extended Core 128 64 IP Master SQBus Local Bus 32 Timers M2 RAM Memory Controller UART 4 TDMs PLL/Clock PLL IPBus 32 JTAG GPIO GIC 8 Hardware Semaphores Ethernet 64 System Interface Internal Local Bus SIU Registers 64 Internal System Bus Direct Slave Interface (DSI) Memory Controller MII/RMII/SMII GPIO Pins Interrupts RS-232 JTAG Port DSI Port 32/64 System Bus 32/64 DMA Bridge Figure 1. MSC8113 Block Diagram Program Sequencer SC140 Core JTAG Power Management Address Register File Address ALU EOnCE Data ALU Register File Data ALU SC140 Core Xa Xb P 64 64 128 M1 RAM Instruction Cache QBus 128 PIC IRQs LIC IRQs MQBus SQBus Local Bus QBus Bank 1 QBus Bank 3 QBC QBus Interface 128 128 64 Notes: 1. The arrows show the data transfer direction. 2. The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines four QBus banks. In addition, the QBC handles internal memory contentions. Figure 2. StarCore(R) SC140 DSP Extended Core Block Diagram MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 3 Pin Assignments 1 1.1 Pin Assignments FC-PBGA Ball Layout Diagrams This section includes diagrams of the MSC8113 package ball grid array layouts and pinout allocation tables. Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 4 Freescale Semiconductor Pin Assignments Top View 2 B 3 VDD 4 GND 5 GND 6 NMI_ OUT 7 GND 8 VDD 9 GND 10 VDD 11 GND 12 VDD 13 GND 14 VDD 15 GND 16 VDD 17 GND 18 VDD 19 GPIO0 20 VDD 21 VDD 22 GND C GND VDD TDO S GPIO28 HCID1 RESET GND VDD GND VDD GND VDD GND GND GPIO30 GPIO2 GPIO1 GPIO7 GPIO3 GPIO5 GPIO6 D TDI EE0 EE1 GND VDDH HCID2 HCID3 GND VDD GND VDD GND VDD VDD GPIO31 GPIO29 VDDH GPIO4 VDDH GND GPIO8 E TCK TRST TMS HRESET GPIO27 HCID0 GND VDD GND VDD GND VDD GND GND VDD GND GND GPIO9 GPIO13 GPIO10 GPIO12 F PO RESET RST CONF NMI HA29 HA22 GND VDD VDD VDD GND VDD GND VDD ETHRX_ ETHTX_ GPIO20 GPIO18 GPIO16 GPIO11 GPIO14 GPIO19 CLK CLK ETHCR S G HA24 HA27 HA25 HA23 HA17 PWE0 VDD VDD BADDR 31 BM0 ABB VDD INT_ OUT VDD CS1 BCTL0 GPIO15 GND GPIO17 GPIO22 H HA20 HA28 VDD HA19 TEST PSD CAS PGTA VDD BM1 ARTRY AACK DBB HTA VDD TT4 CS4 GPIO24 GPIO21 VDD VDDH A31 J HA18 HA26 VDD HA13 GND PSDA BADDR MUX 27 BADDR 30 VDD CLKIN BM2 DBG VDD GND VDD TT3 PSDA10 BCTL1 GPIO23 GND GPIO25 A30 K HA15 HA21 HA16 PWE3 PWE1 POE Res. GND GND GND GND CLKOUT VDD TT2 ALE CS2 GND A26 A29 A28 L HA12 HA14 HA11 VDDH VDDH BADDR BADDR 28 29 GND GND GND VDDH GND GND CS3 VDDH A27 A25 A22 SC M M HD28 HD31 VDDH GND GND GND VDD VDDH GND GND VDDH HB RST VDDH VDDH GND VDDH A24 A21 13 81 N HD26 HD30 HD29 HD24 PWE2 VDDH HWBS 0 HBCS GND GND HRDS BG HCS CS0 PSDWE GPIO26 A23 A20 P HD20 HD27 HD25 HD23 HWBS 3 HWBS 6 HWBS 7 HWBS 2 HWBS 4 HWBS 5 HWBS HCLKIN 1 GND GNDSYN VCCSYN GND GND TA BR TEA PSD VAL DP0 VDDH GND A19 R HD18 VDDH GND HD22 TSZ1 TSZ3 GBL VDD VDD VDD TT0 DP7 DP6 DP3 TS DP2 A17 A18 A16 T HD17 HD21 HD1 HD0 TSZ0 TSZ2 TBST VDD D16 TT1 D21 D23 DP5 DP4 DP1 D30 GND A15 A14 U HD16 HD19 HD2 D2 D3 D6 D8 D9 D11 D14 D15 D17 D19 D22 D25 D26 D28 D31 VDDH A12 A13 V HD3 VDDH GND D0 D1 D4 D5 D7 D10 D12 D13 D18 D20 GND D24 D27 D29 A8 A9 A10 A11 W HD6 HD5 HD4 GND GND VDDH VDDH GND HDST1 HDST0 VDDH GND HD40 VDDH HD33 VDDH HD32 GND GND A7 A6 Y HD7 HD15 VDDH HD9 VDD HD60 HD58 GND VDDH HD51 GND VDDH HD43 GND VDDH GND HD37 HD34 VDDH A4 A5 AA VDD HD14 HD12 HD10 HD63 HD59 GND VDDH HD54 HD52 VDDH GND VDDH HD46 GND HD42 HD38 HD35 A0 A2 A3 AB GND HD13 HD11 HD8 HD62 HD61 HD57 HD56 HD55 HD53 HD50 HD49 HD48 HD47 HD45 HD44 HD41 HD39 HD36 A1 VDD Figure 3. MSC8113 Package, Top View MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 5 Pin Assignments Bottom View 22 B GND 21 VDD 20 VDD 19 GPIO0 18 VDD 17 GND 16 VDD 15 GND 14 VDD 13 GND 12 VDD 11 GND 10 VDD 9 GND 8 VDD 7 GND 6 NMI_ OUT 5 GND 4 GND 3 VDD 2 C GPIO6 GPIO5 GPIO3 GPIO7 GPIO1 GPIO2 GPIO30 GND GND VDD GND VDD GND VDD GND HCID1 GPIO28 S RESET TDO VDD GND D GPIO8 GND VDDH GPIO4 VDDH GPIO29 GPIO31 VDD VDD GND VDD GND VDD GND HCID3 HCID2 VDDH GND EE1 EE0 TDI E GPIO12 GPIO10 GPIO13 GPIO9 GND GND VDD GND GND VDD GND VDD GND VDD GND HCID0 GPIO27 HRESET TMS TRST TCK F GPIO19 GPIO14 GPIO11 GPIO16 GPIO18 GPIO20 ETHTX_ ETHRX_ CLK CLK ETHCR S VDD GND VDD GND VDD VDD VDD GND HA22 HA29 NMI RST CONF PO RESET G GPIO22 GPIO17 GND GPIO15 BCTL0 CS1 VDD INT_ OUT VDD ABB BM0 BADDR 31 VDD VDD PWE0 HA17 HA23 HA25 HA27 HA24 H A31 VDDH VDD GPIO21 GPIO24 CS4 TT4 VDD HTA DBB AACK ARTRY BM1 VDD PGTA PSD CAS TEST HA19 VDD HA28 HA20 J A30 GPIO25 GND GPIO23 BCTL1 PSDA10 TT3 VDD GND VDD DBG BM2 CLKIN VDD BADDR PSDA 27 MUX BADDR 30 GND HA13 VDD HA26 HA18 K A28 A29 A26 GND CS2 ALE TT2 VDD CLKOUT GND GND GND GND Res. POE PWE1 PWE3 HA16 HA21 HA15 L A22 A25 A27 VDDH CS3 GND GND VDDH GND GND GND BADDR BADDR 29 28 VDDH VDDH HA11 HA14 HA12 M A21 A24 VDDH GND VDDH VDDH HB RST SC 81 13 VDDH GND GND VDDH VDD GND GND GND VDDH HD31 HD28 M N A20 A23 GPIO26 PSDWE CS0 HCS BG HRDS GND GND HBCS HWBS 0 HWBS 1 VDDH PWE2 HD24 HD29 HD30 HD26 P A19 GND VDDH DP0 PSD VAL TEA BR TA GND GND VCCSYN GNDSYN GND HCLKIN HWBS 2 HWBS 4 HWBS 5 HWBS 3 HWBS 6 HWBS 7 HD23 HD25 HD27 HD20 R A16 A18 A17 DP2 TS DP3 DP6 DP7 TT0 VDD VDD VDD GBL TSZ3 TSZ1 HD22 GND VDDH HD18 T A14 A15 GND D30 DP1 DP4 DP5 D23 D21 TT1 D16 VDD TBST TSZ2 TSZ0 HD0 HD1 HD21 HD17 U A13 A12 VDDH D31 D28 D26 D25 D22 D19 D17 D15 D14 D11 D9 D8 D6 D3 D2 HD2 HD19 HD16 V A11 A10 A9 A8 D29 D27 D24 GND D20 D18 D13 D12 D10 D7 D5 D4 D1 D0 GND VDDH HD3 W A6 A7 GND GND HD32 VDDH HD33 VDDH HD40 GND VDDH HDST0 HDST1 GND VDDH VDDH GND GND HD4 HD5 HD6 Y A5 A4 VDDH HD34 HD37 GND VDDH GND HD43 VDDH GND HD51 VDDH GND HD58 HD60 VDD HD9 VDDH HD15 HD7 AA A3 A2 A0 HD35 HD38 HD42 GND HD46 VDDH GND VDDH HD52 HD54 VDDH GND HD59 HD63 HD10 HD12 HD14 VDD AB VDD A1 HD36 HD39 HD41 HD44 HD45 HD47 HD48 HD49 HD50 HD53 HD55 HD56 HD57 HD61 HD62 HD8 HD11 HD13 GND Figure 4. MSC8113 Package, Bottom View MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 6 Freescale Semiconductor Pin Assignments 1.2 Signal List By Ball Location Table 1 presents signal list sorted by ball number. Table 1. MSC8113 Signal Listing by Ball Designator Des. B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 Signal Name VDD GND GND NMI_OUT GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GPIO0/CHIP_ID0/IRQ4/ETHTXD0 VDD VDD GND GND VDD TDO SRESET GPIO28/UTXD/DREQ2 HCID1 GND VDD GND VDD GND VDD GND GND GPIO30/TIMER2/TMCLK/SDA GPIO2/TIMER1/CHIP_ID2/IRQ6 Des. C18 C19 C20 C21 C22 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 Signal Name GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1 GPIO7/TDM3RCLK/IRQ5/ETHTXD3 GPIO3/TDM3TSYN/IRQ1/ETHTXD2 GPIO5/TDM3TDAT/IRQ3/ETHRXD3 GPIO6/TDM3RSYN/IRQ4/ETHRXD2 TDI EE0 EE1 GND VDDH HCID2 HCID3/HA8 GND VDD GND VDD GND VDD VDD GPIO31/TIMER3/SCL GPIO29/CHIP_ID3/ETHTX_EN VDDH GPIO4/TDM3TCLK/IRQ2/ETHTX_ER VDDH GND GPIO8/TDM3RDAT/IRQ6/ETHCOL TCK TRST TMS HRESET GPIO27/URXD/DREQ1 HCID0 GND VDD GND VDD MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 7 Pin Assignments Table 1. MSC8113 Signal Listing by Ball Designator (continued) Des. E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G2 G3 G4 G5 Signal Name GND VDD GND GND VDD GND GND GPIO9/TDM2TSYN/IRQ7/ETHMDIO GPIO13/TDM2RCLK/IRQ11/ETHMDC GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC PORESET RSTCONF NMI HA29 HA22 GND VDD VDD VDD GND VDD GND VDD ETHRX_CLK/ETHSYNC_IN ETHTX_CLK/ETHREF_CLK/ETHCLOCK GPIO20/TDM1RDAT GPIO18/TDM1RSYN/DREQ2 GPIO16/TDM1TCLK/DONE1/DRACK1 GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC GPIO19/TDM1RCLK/DACK2 HA24 HA27 HA25 HA23 Des. G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 Signal Name HA17 PWE0/PSDDQM0/PBS0 VDD VDD IRQ3/BADDR31 BM0/TC0/BNKSEL0 ABB/IRQ4 VDD IRQ7/INT_OUT ETHCRS/ETHRXD VDD CS1 BCTL0 GPIO15/TDM1TSYN/DREQ1 GND GPIO17/TDM1TDAT/DACK1 GPIO22/TDM0TCLK/DONE2/DRACK2 HA20 HA28 VDD HA19 TEST PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS VDD BM1/TC1/BNKSEL1 ARTRY AACK DBB/IRQ5 HTA VDD TT4/CS7 CS4 GPIO24/TDM0RSYN/IRQ14 GPIO21/TDM0TSYN VDD MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 8 Freescale Semiconductor Pin Assignments Table 1. MSC8113 Signal Listing by Ball Designator (continued) Des. H21 H22 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 Signal Name VDDH A31 HA18 HA26 VDD HA13 GND PSDAMUX/PGPL5 BADDR27 VDD CLKIN BM2/TC2/BNKSEL2 DBG VDD GND VDD TT3/CS6 PSDA10/PGPL0 BCTL1/CS5 GPIO23/TDM0TDAT/IRQ13 GND GPIO25/TDM0RCLK/IRQ15 A30 HA15 HA21 HA16 PWE3/PSDDQM3/PBS3 PWE1/PSDDQM1/PBS1 POE/PSDRAS/PGPL2 IRQ2/BADDR30 Reserved GND GND GND GND CLKOUT Des. K15 K16 K17 K18 K19 K20 K21 K22 L2 L3 L4 L5 L6 L7 L8 L9 L10 L14 L15 L16 L17 L18 L19 L20 L21 L22 M2 M3 M4 M5 M6 M7 M8 M9 M10 M14 Signal Name VDD TT2/CS5 ALE CS2 GND A26 A29 A28 HA12 HA14 HA11 VDDH VDDH BADDR28 IRQ5/BADDR29 GND GND GND VDDH GND GND CS3 VDDH A27 A25 A22 HD28 HD31 VDDH GND GND GND VDD VDDH GND GND MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 9 Pin Assignments Table 1. MSC8113 Signal Listing by Ball Designator (continued) Des. M15 M16 M17 M18 M19 M20 M21 M22 N2 N3 N4 N5 N6 N7 N8 N9 N10 N14 N15 N16 N17 N18 N19 N20 N21 N22 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 Signal Name VDDH HBRST VDDH VDDH GND VDDH A24 A21 HD26 HD30 HD29 HD24 PWE2/PSDDQM2/PBS2 VDDH HWBS0/HDBS0/HWBE0/HDBE0 HBCS GND GND HRDS/HRW/HRDE BG HCS CS0 PSDWE/PGPL1 GPIO26/TDM0RDAT A23 A20 HD20 HD27 HD25 HD23 HWBS3/HDBS3/HWBE3/HDBE3 HWBS2/HDBS2/HWBE2/HDBE2 HWBS1/HDBS1/HWBE1/HDBE1 HCLKIN GND GNDSYN Des. P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T2 T3 T4 T5 Signal Name VCCSYN GND GND TA BR TEA PSDVAL DP0/DREQ1/EXT_BR2 VDDH GND A19 HD18 VDDH GND HD22 HWBS6/HDBS6/HWBE6/HDBE6/PWE6/PSDDQM6/PBS6 HWBS4/HDBS4/HWBE4/HDBE4/PWE4/PSDDQM4/PBS4 TSZ1 TSZ3 IRQ1/GBL VDD VDD VDD TT0/HA7 IRQ7/DP7/DREQ4 IRQ6/DP6/DREQ3 IRQ3/DP3/DREQ2/EXT_BR3 TS IRQ2/DP2/DACK2/EXT_DBG2 A17 A18 A16 HD17 HD21 HD1/DSISYNC HD0/SWTE MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 10 Freescale Semiconductor Pin Assignments Table 1. MSC8113 Signal Listing by Ball Designator (continued) Des. T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 Signal Name HWBS7/HDBS7/HWBE7/HDBE7/PWE7/PSDDQM7/PBS7 HWBS5/HDBS5/HWBE5/HDBE5/PWE5/PSDDQM5/PBS5 TSZ0 TSZ2 TBST VDD D16 TT1 D21 D23 IRQ5/DP5/DACK4/EXT_BG3 IRQ4/DP4/DACK3/EXT_DBG3 IRQ1/DP1/DACK1/EXT_BG2 D30 GND A15 A14 HD16 HD19 HD2/DSI64 D2 D3 D6 D8 D9 D11 D14 D15 D17 D19 D22 D25 D26 D28 D31 VDDH Des. U21 U22 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 Signal Name A12 A13 HD3/MODCK1 VDDH GND D0 D1 D4 D5 D7 D10 D12 D13 D18 D20 GND D24 D27 D29 A8 A9 A10 A11 HD6 HD5/CNFGS HD4/MODCK2 GND GND VDDH VDDH GND HDST1/HA10 HDST0/HA9 VDDH GND HD40/D40/ETHRXD0 MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 11 Pin Assignments Table 1. MSC8113 Signal Listing by Ball Designator (continued) Des. W15 W16 W17 W18 W19 W20 W21 W22 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA2 AA3 AA4 AA5 AA6 AA7 AA8 Signal Name VDDH HD33/D33/reserved VDDH HD32/D32/reserved GND GND A7 A6 HD7 HD15 VDDH HD9 VDD HD60/D60/ETHCOL/reserved HD58/D58/ETHMDC GND VDDH HD51/D51 GND VDDH HD43/D43/ETHRXD3/reserved GND VDDH GND HD37/D37/reserved HD34/D34/reserved VDDH A4 A5 VDD HD14 HD12 HD10 HD63/D63 HD59/D59/ETHMDIO GND Des. AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 Signal Name VDDH HD54/D54/ETHTX_EN HD52/D52 VDDH GND VDDH HD46/D46/ETHTXT0 GND HD42/D42/ETHRXD2/reserved HD38/D38/reserved HD35/D35/reserved A0 A2 A3 GND HD13 HD11 HD8 HD62/D62 HD61/D61 HD57/D57/ETHRX_ER HD56/D56/ETHRX_DV/ETHCRS_DV HD55/D55/ETHTX_ER/reserved HD53/D53 HD50/D50 HD49/D49/ETHTXD3/reserved HD48/D48/ETHTXD2/reserved HD47/D47/ETHTXD1 HD45/D45 HD44/D44 HD41/D41/ETHRXD1 HD39/D39/reserved HD36/D36/reserved A1 VDD MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 12 Freescale Semiconductor Electrical Characteristics 2 Electrical Characteristics This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC8113 Reference Manual. 2.1 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VDD). In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification never occurs in the same device with a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2 describes the maximum electrical ratings for the MSC8113. Table 2. Absolute Maximum Ratings Rating Core and PLL supply voltage I/O supply voltage Input voltage Maximum operating temperature: Minimum operating temperature Storage temperature range Notes: 1. 2. 3. Symbol VDD VDDH VIN TJ TJ TSTG Value -0.2 to 1.6 -0.2 to 4.0 -0.2 to 4.0 105 -40 -55 to +150 Unit V V V C C C Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. Section 4.5, Thermal Considerations includes a formula for computing the chip junction temperature (TJ). MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 13 Electrical Characteristics 2.2 Recommended Operating Conditions Table 3. Recommended Operating Conditions Rating Symbol VDD VCCSYN VDDH VIN TJ Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Value 1.07 to 1.13 3.135 to 3.465 -0.2 to VDDH+0.2 -40 to 105 Unit V V V C Core and PLL supply voltage: I/O supply voltage Input voltage Operating temperature range: 2.3 Thermal Characteristics Table 4. Thermal Characteristics for the MSC8113 FC-PBGA 20 x 20 mm5 Natural Convection 200 ft/min (1 m/s) airflow 21 15 C/W C/W C/W C/W C/W Table 4 describes thermal characteristics of the MSC8113 for the FC-PBGA packages. Characteristic Symbol Unit Junction-to-ambient1, 2 Junction-to-ambient, four-layer board Junction-to-board (bottom)4 Junction-to-case5 Junction-to-package-top6 Notes: 1. 1, 3 RJA RJA RJB RJC JT 26 19 9 0.9 1 2. 3. 4. 5. 6. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. Section 4.5, Thermal Considerations provides a detailed explanation of these characteristics. 2.4 * * * * DC Electrical Characteristics TA = 25 C VDD = 1.1 V nominal = 1.07-1.13 VDC VDDH = 3.3 V 5% VDC GND = 0 VDC This section describes the DC electrical characteristics for the MSC8113. The measurements in Table 5 assume the following system conditions: Note: The leakage current is measured for nominal VDDH and VDD. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 14 Freescale Semiconductor Electrical Characteristics Table 5. DC Electrical Characteristics Characteristic Input high voltage , all inputs except CLKIN Input low voltage1 CLKIN input high voltage CLKIN input low voltage Input leakage current, VIN = VDDH Tri-state (high impedance off state) leakage current, VIN = VDDH Signal low input current, VIL = 0.8 V Output high voltage, IOH = -2 mA, except open drain pins Output low voltage, IOL= 3.2 mA Internal supply current: * Wait mode * Stop mode Typical power 400 MHz at 1.1 V4 Typical power 300 MHz at 1.1 V4 Notes: 1. 2. 3. 4. 2 1 Symbol VIH VIL VIHC VILC IIN IOZ IL IH VOH VOL IDDW IDDS P Min 2.0 GND 2.4 GND -1.0 -1.0 -1.0 -1.0 2.0 -- -- -- -- -- Typical -- 0 3.0 0 0.09 0.09 0.09 0.09 3.0 0 3753 2903 826 676 Max 3.465 0.8 3.465 0.8 1 1 1 1 -- 0.4 -- -- -- -- Unit V V V V A A A A V V mA mA mW mW Signal high input current, VIH = 2.0 V2 See Figure 5 for undershoot and overshoot voltages. Not tested. Guaranteed by design. Measured for 1.1 V core at 25C junction temperature. The typical power values were calculated using a power calculator configured for three cores performing an EFR code with the device running at the specified operating frequency and a junction temperature of 25C. No peripherals were included. The calculator was created using CodeWarrior(R) 2.5. These values are provided as examples only. Power consumption is application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Chapter 4 of this document and in MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601). VIH VDDH + 17% VDDH + 8% VDDH VIL GND GND - 0.3 V GND - 0.7 V Must not exceed 10% of clock period Figure 5. Overshoot/Undershoot Voltage for VIH and VIL MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 15 Electrical Characteristics 2.5 AC Timings The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF load, except where noted otherwise, and a 50 transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay. When calculating overall loading, also consider additional RC delay. 2.5.1 Output Buffer Impedances Table 6. Output Buffer Impedances Output Buffers Typical Impedance () 50 50 50 System bus Memory controller Parallel I/O Note: These are typical values at 65C. The impedance may vary by 25% depending on device process and operating temperature. 2.5.2 Start-Up Timing Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3 describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the following guidelines when starting up an MSC8113 device: * * * * PORESET and TRST must be asserted externally for the duration of the power-up sequence. See Table 11 for timing. If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up the VDD levels and then the VDDH levels (see Figure 7). CLKIN should start toggling at least 16 cycles (starting after VDDH reaches its nominal level) before PORESET deassertion to guarantee correct device operation (see Figure 6 and Figure 7). CLKIN must not be pulled high during VDDH power-up. CLKIN can toggle during this period. The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which VDD and VDDH are raised together. Figure 7 shows a sequence in which VDDH is raised after VDD and CLKIN begins to toggle as VDDH rises. VDDH = Nominal Value VDD = Nominal Value 1 3.3 V VDDH Nominal Level Voltage 2.2 V 1.1 V o.5 V VDD Nominal Level Time PORESET/TRST Deasserted CLKIN Starts Toggling PORESET/TRST Asserted VDD/VDDH Applied Figure 6. Start-Up Sequence: VDD and VDDH Raised Together MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 16 Freescale Semiconductor Electrical Characteristics VDDH = Nominal VDD = Nominal 1 3.3 V VDDH Nominal Voltage 1.1 V o.5 V VDD Nominal Time PORESET/TRST asserted VDD applied CLKIN starts toggling VDDH applied PORESET/TRST deasserted Figure 7. Start-Up Sequence: VDD Raised Before VDDH with CLKIN Started with VDDH 2.5.3 Clock and Timing Signals The following sections include a description of clock signal characteristics. Table 7 shows the maximum frequency values for internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user must ensure that maximum frequency values are not exceeded. Table 7. Maximum Frequencies Characteristic Core frequency Reference frequency (REFCLK) Internal bus frequency (BLCK) DSI clock frequency (HCLKIN) * Core frequency = 300 MHz * Core frequency = 400 MHz External clock frequency (CLKIN or CLKOUT) Maximum in MHz 300/400 100/133 100/133 HCLKIN (min{70 MHz, CLKOUT}) HCLKIN (min{100 MHz, CLKOUT}) 100/133 Table 8. Clock Frequencies 300 MHz Device Characteristics CLKIN frequency BCLK frequency Reference clock (REFCLK) frequency Output clock (CLKOUT) frequency SC140 core clock frequency Note: 400 MHz Device Min 20 40 40 40 200 Symbol Min FCLKIN FBCLK FREFCLK FCLKOUT FCORE 20 40 40 40 200 Max 100 100 100 100 300 Max 133.3 133.3 133.3 133.3 400 The rise and fall time of external clocks should be 3 ns maximum Table 9. System Clock Parameters Characteristic Phase jitter between BCLK and CLKIN CLKIN frequency CLKIN slope PLL input clock (after predivider) Min -- 20 -- 20 Max 0.3 see Table 8 3 100 Unit ns MHz ns MHz MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 17 Electrical Characteristics Table 9. System Clock Parameters (continued) Characteristic PLL output frequency (VCO output) * 300 MHz core * 400 MHz core CLKOUT frequency jitter1 CLKOUT phase jitter1 with CLKIN phase jitter of 100 ps. Notes: 1. 2. Peak-to-peak. Not tested. Guaranteed by design. Min 800 Max 1200 1600 Unit MHz MHz MHz ps ps -- -- 200 500 2.5.4 * * * * * * Reset Timing Power-on reset (PORESET) External hard reset (HRESET) External soft reset (SRESET) Software watchdog reset Bus monitor reset Host reset command through JTAG The MSC8113 has several inputs to the reset logic: All MSC8113 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources. Table 10. Reset Sources Name Power-on reset (PORESET) Direction Input Description Initiates the power-on reset flow that resets the MSC8113 and configures various attributes of the MSC8113. On PORESET, the entire MSC8113 device is reset. SPLL states is reset, HRESET and SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64 bits port or a System Bus 64 bits port are configured only when PORESET is asserted. Initiates the hard reset flow that configures various attributes of the MSC8113. While HRESET is asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The most configurable features are reconfigured. These features are defined in the 32-bit hard reset configuration word described in Hard Reset Configuration Word section of the Reset chapter in the MSC8113 Reference Manual. Initiates the soft reset flow. The MSC8113 detects an external assertion of SRESET only if it occurs while the MSC8113 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is driven, the SC140 extended cores are reset, and system configuration is maintained. When the MSC8113 watchdog count reaches zero, a software watchdog reset is signalled. The enabled software watchdog event then generates an internal hard reset sequence. When the MSC8113 bus monitor count reaches zero, a bus monitor hard reset is asserted. The enabled bus monitor event then generates an internal hard reset sequence. When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the soft reset signal and an internal soft reset sequence is generated. External hard reset (HRESET) Input/ Output External soft reset (SRESET) Software watchdog reset Bus monitor reset Host reset command through the TAP Input/ Output Internal Internal Internal Table 11 summarizes the reset actions that occur as a result of the different reset sources. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 18 Freescale Semiconductor Electrical Characteristics Table 11. Reset Actions for Each Reset Source Power-On Reset (PORESET) Reset Action/Reset Source External only Configuration pins sampled (Refer to Section 2.5.4.1 for details). SPLL state reset System reset configuration write through the DSI System reset configuration write though the system bus HRESET driven SIU registers reset IPBus modules reset (TDM, UART, Timers, DSI, IPBus master, GIC, HS, and GPIO) SRESET driven SC140 extended cores reset MQBS reset Yes Yes Yes Yes Yes Yes Yes Hard Reset (HRESET) External or Internal (Software Watchdog or Bus Monitor) No No No Yes Yes Yes Yes Soft Reset (SRESET) JTAG Command: EXTEST, CLAMP, or HIGHZ No No No No No No Yes External No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Depends on command Yes Yes 2.5.4.1 Power-On Reset (PORESET) Pin Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after VDD and VDDH are both at their nominal levels. 2.5.4.2 * * Reset Configuration The MSC8113 has two mechanisms for writing the reset configuration: Through the direct slave interface (DSI) Through the system bus. When the reset configuration is written through the system bus, the MSC8113 acts as a configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is written, a default configuration word is applied. Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the Reset Configuration Mode and boot and operating conditions: * * * * * * * * RSTCONF CNFGS DSISYNC DSI64 CHIP_ID[0-3] BM[0-2] SWTE MODCK[1-2] MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 19 Electrical Characteristics 2.5.4.3 Reset Timing Tables Table 12 and Figure 8 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or through the system bus. Table 12. Timing for a Reset Configuration Write through the DSI or System Bus No. 1 Characteristics Required external PORESET duration minimum * CLKIN = 20 MHz * CLKIN = 100 MHz (300 MHz core) * CLKIN = 133 MHz (400 MHz core) Delay from deassertion of external PORESET to deassertion of internal PORESET * CLKIN = 20 MHz to 133 MHz Delay from de-assertion of internal PORESET to SPLL lock * CLKIN = 20 MHz (RDF = 1) * CLKIN = 100 MHz (RDF = 1) (300 MHz core) * CLKIN = 133 MHz (RDF = 2) (400 MHz core) Delay from SPLL to HRESET deassertion * REFCLK = 40 MHz to 133 MHz Delay from SPLL lock to SRESET deassertion * REFCLK = 40 MHz to 133 MHz Setup time from assertion of RSTCONF, CNFGS, DSISYNC, DSI64, CHIP_ID[0-3], BM[0-2], SWTE, and MODCK[1-2] before deassertion of PORESET Hold time from deassertion of PORESET to deassertion of RSTCONF, CNFGS, DSISYNC, DSI64, CHIP_ID[0-3], BM[0-2], SWTE, and MODCK[1-2] Timings are not tested, but are guaranteed by design. Expression 16/CLKIN Min 800 160 120 Max -- -- -- Unit ns ns ns 2 1024/CLKIN 6.17 6400/(CLKIN/RDF) (PLL reference clock-division factor) 320 64 96 3.08 3.10 3 51.2 320 64 96 12.8 12.88 -- s s s s s s ns 3 5 6 7 512/REFCLK 515/REFCLK 8 5 -- ns Note: 1 RSTCONF, CNFGS, DSISYNC, DSI64 CHIP_ID[0-3], BM[0-2], SWTE, MODCK[1-2] pins are sampled Host programs Reset Configuration Word SPLL is locked (no external indication) PORESET Input PORESET Internal 1+2 MODCK[3-5] HRESET Output (I/O) 2 3 SRESET Output (I/O) Reset configuration write sequence during this period. SPLL locking period 5 6 Figure 8. Timing Diagram for a Reset Configuration Write MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 20 Freescale Semiconductor Electrical Characteristics 2.5.5 2.5.5.1 System Bus Access Timing Core Data Transfers Generally, all MSC8113 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The REFCLK is the CLKIN signal. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 13 shows. Table 13. Tick Spacing for Memory Controller Signals Tick Spacing (T1 Occurs at the Rising Edge of REFCLK) BCLK/SC140 clock T2 1:4, 1:6, 1:8, 1:10 1:3 1:5 1/4 REFCLK 1/6 REFCLK 2/10 REFCLK T3 1/2 REFCLK 1/2 REFCLK 1/2 REFCLK T4 3/4 REFCLK 4/6 REFCLK 7/10 REFCLK Figure 9 is a graphical representation of Table 13. REFCLK T1 REFCLK T1 T2 T3 T4 T2 T3 T4 for 1:3 for 1:4, 1:6, 1:8, 1:10 REFCLK T1 T2 T3 T4 for 1:5 Figure 9. Internal Tick Spacing for Memory Controller Signals The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration. The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the REFCLK rising edge. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 21 Electrical Characteristics Table 14. AC Timing for SIU Inputs No. 10 11a 11b 11c 11d Characteristic Hold time for all signals after the 50% level of the REFCLK rising edge ARTRY/ABB set-up time before the 50% level of the REFCLK rising edge DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK rising edge AACK set-up time before the 50% level of the REFCLK rising edge TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK rising edge * Data-pipeline mode * Non-pipeline mode Data bus set-up time before REFCLK rising edge in Normal mode * Data-pipeline mode * Non-pipeline mode Data bus set-up time before the 50% level of the REFCLK rising edge in ECC and PARITY modes * Data-pipeline mode * Non-pipeline mode DP set-up time before the 50% level of the REFCLK rising edge * Data-pipeline mode * Non-pipeline mode TS and Address bus set-up time before the 50% level of the REFCLK rising edge * Extra cycle mode (SIUBCR[EXDD] = 0) * No extra cycle mode (SIUBCR[EXDD] = 1) Address attributes: TT/TBST/TSZ/GBL set-up time before the 50% level of the REFCLK rising edge * Extra cycle mode (SIUBCR[EXDD] = 0) * No extra cycle mode (SIUBCR[EXDD] = 1) PUPMWAIT signal set-up time before the 50% level of the REFCLK rising edge IRQx setup time before the 50% level; of the REFCLK rising edge3 IRQx minimum pulse width3 1. 2. 3. Ref = CLKIN at 1.1 V and 100/133 MHz 0.5 3.1 3.6 3.0 Units ns ns ns ns 3.5 4.4 1.9 4.2 ns ns ns ns 12 131 2.0 8.2 2.0 7.9 ns ns ns ns 141 15a 4.2 5.5 ns ns 15b 3.7 4.8 3.7 4.0 6.0 + TREFCLK ns ns ns ns ns 16 17 18 Notes: Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings. Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge. Guaranteed by design. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 22 Freescale Semiconductor Electrical Characteristics Table 15. AC Timing for SIU Outputs No. 302 31 32a Characteristic Minimum delay from the 50% level of the REFCLK for all signals PSDVAL/TEA/TA max delay from the 50% level of the REFCLK rising edge Address bus max delay from the 50% level of the REFCLK rising edge * Multi-master mode (SIUBCR[EBM] = 1) * Single-master mode (SIUBCR[EBM] = 0) Address attributes: TT[0-1]/TBST/TSZ/GBL max delay from the 50% level of the REFCLK rising edge Address attributes: TT[2-4]/TC max delay from the 50% level of the REFCLK rising edge BADDR max delay from the 50% level of the REFCLK rising edge Data bus max delay from the 50% level of the REFCLK rising edge * Data-pipeline mode * Non-pipeline mode DP max delay from the 50% level of the REFCLK rising edge * Data-pipeline mode * Non-pipeline mode Memory controller signals/ALE/CS[0-4] max delay from the 50% level of the REFCLK rising edge DBG/BG/BR/DBB max delay from the 50% level of the REFCLK rising edge AACK/ABB/TS/CS[5-7] max delay from the 50% level of the REFCLK rising edge 1. 2. 3. Bus Speed in MHz3 Ref = CLKIN at 1.1 V and 100/ 133 MHz 0.9 6.0 6.4 5.3 6.4 6.9 5.2 4.8 7.1 6.0 7.5 5.1 6.0 5.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns 32b 32c 32d 33a 33b 34 35a 35b Notes: Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except where otherwise specified. The load for specification 30 is 10 pF. The load for the other specifications in this table is 20 pF. For a 15 pF load, subtract 0.3 ns from the listed value. The maximum bus frequency depends on the mode: * In 60x-compatible mode connected to another MSC8113 device, the frequency is determined by adding the input and output longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on. * In single-master mode, the frequency depends on the timing of the devices connected to the MSC8113. * To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the SIUMCR[BDD] bit. See the SIU chapter in the MSC8113 Reference Manual for details. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 23 Electrical Characteristics REFCLK 10 AACK/ARTRY/TA/TEA/DBG/BG/BR PSDVAL/ABB/DBB inputs 11 10 12 Data bus inputs--normal mode 10 Data bus inputs--ECC and parity modes DP inputs Address bus/TS /TT[0-4]/TC[0-2]/ TBST/TSZ[0-3]/GBL inputs PUPMWAIT input 13 14 15 16 17 IRQx inputs 30 Min delay for all output pins 31 PSDVAL/TEA/TA outputs Address bus/TT[0-4]/TC[0-2]/TBST/TSZ[0-3]/GBL outputs 32a/b 18 10 BADDR outputs 32c Data bus outputs DP outputs 33a 33b Memory controller/ALE outputs 34 35 AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs Figure 10. SIU Timing Diagram MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 24 Freescale Semiconductor Electrical Characteristics 2.5.5.2 CLKIN to CLKOUT Skew Table 16. CLKOUT Skew Table 17 describes the CLKOUT-to-CLKIN skew timing. No. 20 21 23 Rise-to-rise skew Fall-to-fall skew Characteristic Min1 0.0 -1.5 2.2 2.2 3.3 3.3 Max1 0.95 1.0 -- -- -- -- Units ns ns ns ns ns ns CLKOUT phase (1.1 V, 133 MHz) * Phase high * Phase low CLKOUT phase (1.1 V, 100 MHz) * Phase high * Phase low 1. 2. 3. 4. 24 Notes: A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN. Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes. CLKOUT skews are measured using a load of 10 pF. CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode. For designs that use the CLKOUT synchronization mode, use the skew values listed in Table 16 to adjust the rise-to-fall timing values specified for CLKIN synchronization. Figure 11 shows the relationship between the CLKOUT and CLKIN timings. CLKIN CLKOUT 20 21 Figure 11. CLKOUT and CLKIN Signals. 2.5.5.3 DMA Data Transfers Table 17. DMA Signals Ref = CLKIN Table 17 describes the DMA signal timing. No. 37 38 39 40 41 Characteristic Min DREQ set-up time before the 50% level of the falling edge of REFCLK DREQ hold time after the 50% level of the falling edge of REFCLK DONE set-up time before the 50% level of the rising edge of REFCLK DONE hold time after the 50% level of the rising edge of REFCLK DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge 5.0 0.5 5.0 0.5 0.5 Units Max -- -- -- -- 7.5 ns ns ns ns ns The DREQ signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ according to the timings in Table 17. Figure 12 shows synchronous peripheral interaction. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 25 Electrical Characteristics REFCLK 38 37 DREQ 40 39 DONE 41 DACK/DONE/DRACK Figure 12. DMA Signals 2.5.6 DSI Timing The timings in the following sections are based on a 20 pF capacitive load. 2.5.6.1 No. 100 101 102 DSI Asynchronous Mode Table 18. DSI Asynchronous Mode Timing Characteristics Attributes1 set-up time before strobe (HWBS[n]) assertion Attributes1 hold time after data strobe deassertion Read/Write data strobe deassertion width: * DCR[HTAAD] = 1 -- Consecutive access to the same DSI -- Different device with DCR[HTADT] = 01 -- Different device with DCR[HTADT] = 10 -- Different device with DCR[HTADT] = 11 * DCR[HTAAD] = 0 Read data strobe deassertion to output data high impedance Read data strobe assertion to output data active from high impedance Output data hold time after read data strobe deassertion Read/Write data strobe assertion to HTA active from high impedance Output data valid to HTA assertion Read/Write data strobe assertion to HTA valid2 Read/Write data strobe deassertion to output HTA high impedance. (DCR[HTAAD] = 0, HTA at end of access released at logic 0) Read/Write data strobe deassertion to output HTA deassertion. (DCR[HTAAD] = 1, HTA at end of access released at logic 1) Read/Write data strobe deassertion to output HTA high impedance. (DCR[HTAAD] = 1, HTA at end of access released at logic 1 * DCR[HTADT] = 01 * DCR[HTADT] = 10 * DCR[HTADT] = 11 Read/Write data strobe assertion width Host data input set-up time before write data strobe deassertion Host data input hold time after write data strobe deassertion 1. 2. 3. Min 1.5 1.3 Max -- -- -- Unit ns ns 1.8 + TREFCLK 5 + TREFCLK 5 + (1.5 x TREFCLK) 5 + (2.5 x TREFCLK) 1.8 + TREFCLK -- 2.0 2.2 2.2 3.2 -- -- -- -- 5 + TREFCLK 5 + (1.5 x TREFCLK) 5 + (2.5 x TREFCLK) 1.8 + TREFCLK 1.0 1.7 -- -- -- 8.5 -- -- -- -- 7.4 6.5 6.5 ns ns ns ns ns ns ns ns ns ns ns ns ns 103 104 105 106 107 108 109 110 111 ns ns ns ns ns ns 112 201 202 Notes: Attributes refers to the following signals: HCS, HA[11-29], HCID[0-4], HDST, HRW, HRDS, and HWBSn. This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design. All values listed in this table are tested or guaranteed by design. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 26 Freescale Semiconductor Electrical Characteristics Figure 13 shows DSI asynchronous read signals timing. HCS HA[11-29] HCID[0-4] HDST HRW1 HWBSn2 100 101 112 HDBSn1 HRDS2 102 103 107 104 HD[0-63] 106 105 109 HTA3 108 110 HTA4 111 Notes: 1. 2. 3. 4. Used for single-strobe mode access. Used for dual-strobe mode access. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation. Figure 13. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 27 Electrical Characteristics Figure 14 shows DSI asynchronous write signals timing. HCS HA[11-29] HCID[0-4] HDST HRW1 HRDS2 100 101 112 HDBSn HWBSn2 201 202 HD[0-63] 109 1 102 106 HTA3 108 110 HTA4 111 Notes: 1. 2. 3. 4. Used for single-strobe mode access. Used for dual-strobe mode access. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation. Figure 14. Asynchronous Single- and Dual-Strobe Modes Write Timing Diagram Figure 15 shows DSI asynchronous broadcast write signals timing. HCS HA[11-29] HCID[0-4] HDST HRW1 HRDS2 100 112 101 HWBSn HDBSn1 2 102 201 202 HD[0-63] Notes: 1. 2. Used for single-strobe mode access. Used for dual-strobe mode access. Figure 15. Asynchronous Broadcast Write Timing Diagram MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 28 Freescale Semiconductor Electrical Characteristics 2.5.6.2 DSI Synchronous Mode Table 19. DSI Inputs in Synchronous Mode 1.1 V Core No. 120 121 122 123 124 125 126 127 Notes: HCLKIN cycle time1,2 HCLKIN high pulse width HCLKIN low pulse width Characteristic Expression Min HTC (0.5 0.1) x HTC (0.5 0.1) x HTC -- -- -- -- -- 10.0 4.0 4.0 1.2 0.6 1.3 1.2 1.5 Units Max 55.6 33.3 33.3 -- -- -- -- -- ns ns ns ns ns ns ns ns HA[11-29] inputs set-up time HD[0-63] inputs set-up time HCID[0-4] inputs set-up time All other inputs set-up time All inputs hold time 1. 2. Values are based on a frequency range of 18-100 MHz. Refer to Table 7 for HCLKIN frequency limits. Table 20. DSI Outputs in Synchronous Mode 1.1 V Core No. 128 129 130 131 132 133 134 135 Characteristic Min HCLKIN high to HD[0-63] output active HCLKIN high to HD[0-63] output valid HD[0-63] output hold time HCLKIN high to HD[0-63] output high impedance HCLKIN high to HTA output active HCLKIN high to HTA output valid HTA output hold time HCLKIN high to HTA high impedance 2.0 -- 1.7 -- 2.2 -- 1.7 -- Units Max -- 7.6 -- 8.3 -- 7.4 -- 7.5 ns ns ns ns ns ns ns ns MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 29 Electrical Characteristics 120 122 HCLKIN 123 HA[11-29] input signals 124 HD[0-63] input signals 125 HCID[0-4] input signals 126 All other input signals 129 121 127 127 127 127 131 130 HD[0-63] output signals ~~ ~~ 128 133 132 135 134 Figure 16. DSI Synchronous Mode Signals Timing Diagram 2.5.7 TDM Timing Table 21. TDM Timing 1.1 V Core No. 300 301 302 303 304 305 306 307 308 309 310 Notes: TDMxRCLK/TDMxTCLK Characteristic Expression Min TC1 (0.5 0.1) x TC (0.5 0.1) x TC 16 7 7 1.3 1.0 2.8 -- 2.5 -- -- 2.5 ~ ~ HTA output signal Units Max -- -- -- -- -- -- 10.0 -- 10.7 9.7 -- ns ns ns ns ns ns ns ns ns ns ns TDMxRCLK/TDMxTCLK high pulse width TDMxRCLK/TDMxTCLK low pulse width TDM receive all input set-up time TDM receive all input hold time TDMxTCLK high to TDMxTDAT/TDMxRCLK output active2,3 TDMxTCLK high to TDMxTDAT/TDMxRCLK output All output hold time4 TDMxTCLK high to TDmXTDAT/TDMxRCLK output high impedance2,3 TDMxTCLK high to TDMXTSYN output valid2 TDMxTSYN output hold time4 1. 2. 3. 4. Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz. Devices operating at 300 MHz are limited to a maximum TDMxRCLK/TDMxTCLK frequency of 50 MHz. Values are based on 20 pF capacitive load. When configured as an output, TDMxRCLK acts as a second data link. See the MSC8113 Reference Manual for details. Values are based on 10 pF capacitive load. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 30 Freescale Semiconductor Electrical Characteristics 300 301 TDMxRCLK 304 303 TDMxRDAT 304 302 303 TDMxRSYN Figure 17. TDM Inputs Signals 300 301 TDMxTCLK 306 302 308 ~~ ~~ 305 TDMxTDAT TDMxRCLK 309 TDMxTSYN 307 310 Figure 18. TDM Output Signals MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 31 2.5.8 UART Timing Table 22. UART Timing Un it ns ns ns No. 400 401 402 Characteristics URXD and UTXD inputs high/low duration URXD and UTXD inputs rise/fall time UTXD output rise/fall time Expression 16 x TREFCLK Min 160.0 Max -- 10 10 401 401 UTXD, URXD inputs 400 400 Figure 19. UART Input Timing 402 402 UTXD output Figure 20. UART Output Timing 2.5.9 Timer Timing Table 23. Timer Timing Ref = CLKIN No. 500 501 502 503 TIMERx frequency TIMERx Input high period TIMERx Output low period Characteristics Min 10.0 4.0 4.0 3.1 Unit Max -- -- -- 9.5 ns ns ns ns TIMERx Propagations delay from its clock input MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 32 Freescale Semiconductor 500 501 502 TIMERx (Input) 503 TIMERx (Output) Figure 21. Timer Timing 2.5.10 2.5.10.1 Ethernet Timing Management Interface Timing Table 24. Ethernet Controller Management Interface Timing No. 801 802 Characteristics ETHMDIO to ETHMDC rising edge set-up time ETHMDC rising edge to ETHMDIO hold time Min 10 10 Max -- -- Unit ns ns ETHMDC 801 802 ETHMDIO Valid Figure 22. MDIO Timing Relationship to MDC MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 33 2.5.10.2 No. 803 804 805 MII Mode Timing Table 25. MII Mode Signal Timing Characteristics Min 3.5 3.5 1 Max -- -- 14.6 Unit ns ns ns ETHRX_DV, ETHRXD[0-3], ETHRX_ER to ETHRX_CLK rising edge set-up time ETHRX_CLK rising edge to ETHRX_DV, ETHRXD[0-3], ETHRX_ER hold time ETHTX_CLK to ETHTX_EN, ETHTXD[0-3], ETHTX_ER output delay ETHRX_CLK 803 ETHRX_DV ETHRXD[0-3] ETHRX_ER Valid 804 ETHTX_CLK 805 ETHTX_EN ETHTXD[0-3] ETHTX_ER Valid Valid Figure 23. MII Mode Signal Timing 2.5.10.3 RMII Mode Table 26. RMII Mode Signal Timing 1.1 V Core No. 806 807 811 Characteristics Min ETHTX_EN,ETHRXD[0-1], ETHCRS_DV, ETHRX_ER to ETHREF_CLK rising edge set-up time ETHREF_CLK rising edge to ETHRXD[0-1], ETHCRS_DV, ETHRX_ER hold time ETHREF_CLK rising edge to ETHTXD[0-1], ETHTX_EN output delay. 1.6 1.6 3 Unit Max -- -- 12.5 ns ns ns ETHREF_CLK 806 ETHCRS_DV ETHRXD[0-1] ETHRX_ER 807 Valid 811 ETHTX_EN ETHTXD[0-1] Valid Valid Figure 24. RMII Mode Signal Timing MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 34 Freescale Semiconductor 2.5.10.4 SMII Mode Table 27. SMII Mode Signal Timing No. 808 809 810 Notes: Characteristics ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay 1. 2. Measured using a 5 pF load. Measured using a 15 pF load. Min 1.0 1.0 1.51 Max -- -- 6.02 Unit ns ns ns ETHCLOCK 808 ETHSYNC_IN ETHRXD 809 Valid 810 ETHSYNC ETHTXD Valid Valid Figure 25. SMII Mode Signal Timing 2.5.11 GPIO Timing Table 28. GPIO Timing Ref = CLKIN No. 601 602 603 604 605 Characteristics Min REFCLK edge to GPIO out valid (GPIO out delay time) REFCLK edge to GPIO out not valid (GPIO out hold time) REFCLK edge to high impedance on GPIO out GPIO in valid to REFCLK edge (GPIO in set-up time) REFCLK edge to GPIO in not valid (GPIO in hold time) -- 1.1 -- 3.5 0.5 Unit Max 6.1 -- 5.4 -- -- ns ns ns ns ns REFCLK 601 603 GPIO (Output) High Impedance 602 604 GPIO (Input) 605 Valid Figure 26. GPIO Timing MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 35 2.5.12 EE Signals Table 29. EE Pin Timing Number 65 66 Notes: 1. 2. Characteristics EE0 (input) EE1 (output) Type Asynchronous Synchronous to Core clock Min 4 core clock periods 1 core clock period The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset. Refer to Table 1-4 on page 1-6 for details on EE pin functionality. Figure 27 shows the signal behavior of the EE pins. 65 EE0 in 66 EE1 out Figure 27. EE Pin Timing 2.5.13 JTAG Signals Table 30. JTAG Timing No. 700 701 702 Characteristics TCK frequency of operation (1/(TC x 4); maximum 25 MHz) TCK cycle time TCK clock pulse width measured at VM = 1.6 V * High * Low TCK rise and fall times Boundary scan input data set-up time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST assert time TRST set-up time to TCK low All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port. All frequencies Min 0.0 40.0 20.0 16.0 0.0 5.0 20.0 0.0 0.0 5.0 20.0 0.0 0.0 100.0 30.0 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max 25 -- -- -- 3.0 -- -- 30.0 30.0 -- -- 20.0 20.0 -- -- 703 704 705 706 707 708 709 710 711 712 713 Note: MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 36 Freescale Semiconductor 701 702 TCK (Input) VIH 703 VM VIL 703 VM Figure 28. Test Clock Input Timing Diagram TCK (Input) VIH VIL 704 705 Data Inputs 706 Data Outputs 707 Data Outputs Input Data Valid Output Data Valid Figure 29. Boundary Scan (JTAG) Timing Diagram VIH VIL 708 TDI TMS (Input) 710 TDO (Output) 711 TDO (Output) Output Data Valid Input Data Valid 709 TCK (Input) Figure 30. Test Access Port Timing Diagram TCK (Input) 713 TRST (Input) 712 Figure 31. TRST Timing Diagram MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 37 Hardware Design Considerations 3 3.1 * * * Hardware Design Considerations Start-up Sequencing Recommendations Assert PORESET and TRST before applying power and keep the signals driven low until the power reaches the required minimum power levels. This can be implemented via weak pull-down resistors. CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN must start toggling before the deassertion of PORESET and after both power supplies have reached nominal voltage levels. If possible, bring up VDD/VCCSYN and VDDH together. If it is not possible, raise VDD/VCCSYN first and then bring up VDDH. VDDH should not exceed VDD/VCCSYN until VDD/VCCSYN reaches its nominal voltage level. Similarly, bring both voltage levels down together. If that is not possible reverse the power-up sequence, with VDDH going down first and then VDD/VCCSYN. This recommended power sequencing for the MSC8113 is different from the MSC8102. The following sections discuss areas to consider when the MSC8113 device is designed into a system. Use the following guidelines for start-up and power-down sequences: Note: External voltage applied to any input line must not exceed the I/O supply VDDH by more than 0.8 V at any time, including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes. This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the system during start-up. After power-up, VDDH must not exceed VDD/VCCSYN by more than 2.6 V. 3.2 Power Supply Design Considerations When implementing a new design, use the guidelines described in the MSC8113 Design Checklist (AN3374 for optimal system performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937) provides detailed design information. Figure 32 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved by using the following guidelines: * For the core supply, use a voltage regulator rated at 1.1 V with nominal rating of at least 3 A. This rating does not reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has better voltage recovery time than supplies with lower current ratings. Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 32 shows three capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount at least one of the capacitors directly below the MSC8113 device. * Maximum IR drop of 15 mV at 1 A 1.1 V Power supply or Voltage Regulator Lmax = 2 cm One 0.01 F capacitor for every 3 core supply pads. MSC8113 (Imin = 3 A) + - Bulk/Tantalum capacitors with low ESR and ESL Note: Use at least three capacitors. Each capacitor must be at least 150 F. High frequency capacitors (very low ESR and ESL) Figure 32. Core Power Supply Decoupling MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 38 Freescale Semiconductor Hardware Design Considerations Each VCC and VDD pin on the MSC8113 device should have a low-impedance path to the board power supply. Similarly, each GND pin should have a low-impedance path to the ground plane. The power supply pins drive distinct groups of logic on the chip. The VCC power supply should have at least four 0.1 F by-pass capacitors to ground located as closely as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the MSC8113 have fast rise and fall times. PCB trace interconnection length should be minimized to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins: VCCSYN-GNDSYN. To ensure internal clock stability, filter the power to the VCCSYN input with a circuit similar to the one in Figure 33. For optimal noise filtering, place the circuit as close as possible to VCCSYN. The 0.01-F capacitor should be closest to VCCSYN, followed by the 10-F capacitor, the 10-nH inductor, and finally the 10- resistor to VDD. These traces should be kept short and direct. Provide an extremely low impedance path to the ground plane for GNDSYN. Bypass GNDSYN to VCCSYN by a 0.01-F capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of the PCB aligned with the depopulated void on the MSC8113 located in the square defined by positions, L11, L12, L13, M11, M12, M13, N11, N12, and N13. VDD 10 10nH 10 F 0.01 F VCCSYN Figure 33. VCCSYN Bypass 3.3 * * * * * * * * Connectivity Guidelines If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must pulled up and all the rest of the DSI signals can be disconnected. When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled either up or down, depending on design requirements. HDST can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the DCR[DSRFA] bit is set. When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, pull up HWBS[1-3]/HDBS[1-3]/HWBE[1-3]/ HDBE[1-3] and HWBS[4-7]/HDBS[4-7]/HWBE[4-7]/HDBE[4-7]/PWE[4-7]/PSDDQM[4-7]/PBS[4-7]. When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared, HWBS[1-3]/HDBS[1-3]/HWBE[1-3]/HDBE[1-3] must be pulled up. When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or pulled up. The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK. In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0): -- BG, DBG, and TS can be left unconnected. -- EXT_BG[2-3], EXT_DBG[2-3], and GBL can be left unconnected if they are multiplexed to the system bus functionality. For any other functionality, connect the signal lines based on the multiplexed functionality. -- BR must be pulled up. -- EXT_BR[2-3] must be pulled up if multiplexed to the system bus functionality. Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to VDDH or GND, except for the following: MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 39 Hardware Design Considerations * * Note: * * If there is an external bus master (BCR[EBM] = 1): -- BR, BG, DBG, and TS must be pulled up. -- EXT_BR[2-3], EXT_BG[2-3], and EXT_DBG[2-3] must be pulled up if multiplexed to the system bus functionality. In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In other modes, they must be pulled up. The MSC8113 does not support DLL-enabled mode. For the following two clock schemes, ensure that the DLL is disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set). If no system synchronization is required (for example, the design does not use SDRAM), you can use any of the available clock modes. In the CLKIN synchronization mode, use the following connections: -- Connect the oscillator output through a buffer to CLKIN. -- Connect the CLKIN buffer output to the slave device (for example, SDRAM) making sure that the delay path between the clock buffer to the MSC8113 and the SDRAM is equal (that is, has a skew less than 100 ps). -- Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31. See the Clock chapter in the MSC8113 Reference Manual for details. If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected. Otherwise, it should be pulled up. The following signals: SWTE, DSISYNC, DSI64, MODCK[1-2], CNFGS, CHIPID[0-3], RSTCONF and BM[0-2] are used to configure the MSC8113 and are sampled on the deassertion of the PORESET signal. Therefore, they should be tied to GND or VDDH or through a pull-down or a pull-up resistor until the deassertion of the PORESET signal. When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive) signals must be pulled up. When the Ethernet controller is enabled and the SMII mode is selected, GPIO10 and GPIO14 must not be connected externally to any signal line. For details on configuration, see the MSC8113 User's Guide and MSC8113 Reference Manual. For additional information, refer to the MSC8113 Design Checklist (ANxxxx). Note: * * * * Note: 3.4 External SDRAM Selection The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However, because of differences in timing characteristics among various SDRAM manufacturers, you may have use a faster speed rated SDRAM to assure efficient data transfer across the bus. For example, for 133 MHz operation, you may have to use 133 or 166 MHz SDRAM. Always perform a detailed timing analysis using the MSC8113 bus timing values and the manufacturer specifications for the SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is usually given for a load of 30 pF. Scale the number to your specific board load using the typical scaling number provided by the SDRAM manufacturer. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 40 Freescale Semiconductor Ordering Information 3.5 Thermal Considerations TJ = TA + (RJA x PD) Eqn. 1 An estimation of the chip-junction temperature, TJ, in C can be obtained from the following: where TA = ambient temperature near the package (C) RJA = junction-to-ambient thermal resistance (C/W) PD = PINT + PI/O = power dissipation in the package (W) PINT = IDD x VDD = internal power dissipation (W) PI/O = power dissipated from device on output pins (W) The power dissipation values for the MSC8113 are listed in Table 2-3. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. The value that more closely approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB). The value obtained using a single layer board is appropriate for tightly packed PCB configurations. The value obtained using a board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm2 with natural convection) and well separated components. Based on an estimation of junction temperature using this technique, determine whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the device thermal junction temperature below its maximum. If TJ appears to be too high, either lower the ambient temperature or the power dissipation of the chip. You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on a spot on the device case that is painted black. The MSC8113 device case surface is too shiny (low emissivity) to yield an accurate infrared temperature measurement. Use the following equation to determine TJ: TJ = TT + (JA x PD) where TT = thermocouple (or infrared) temperature on top of the package (C) JA = thermal characterization parameter (C/W) PD = power dissipation in the package (W) Note: See MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601/D). Eqn. 2 4 Ordering Information Core Voltage 1.1 V Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order. Operating Temperature -40 to 105C Part MSC8113 Package Type Flip Chip Plastic Ball Grid Array (FC-PBGA) Core Frequency (MHz) 300 400 Order Number Lead-Free MSC8113TVT3600V MSC8113TVT4800V Lead-Bearing MSC8113TMP3600V MSC8113TMP4800V MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 41 Package Information 5 Package Information Notes: 1. All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M-1994. 3. Features are symmetrical about the package center lines unless dimensioned otherwise. 4. Maximum solder ball diameter measured parallel to Datum A. 5. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 6. Parallelism measurement shall exclude any effect of mark on top surface of package. 7. Capacitors may not be present on all devices. 8. Caution must be taken not to short capacitors or exposed metal capacitor pads on package top. 9. FC CBGA (Ceramic) package code: 5238. FC PBGA (Plastic) package code: 5263. 10.Pin 1 indicator can be in the form of number 1 marking or an "L" shape marking. Figure 34. MSC8113 Mechanical Information, 431-pin FC-PBGA Package 6 * * * * Product Documentation MSC8113 Technical Data Sheet (MSC8113). Details the signals, AC/DC characteristics, clock signal characteristics, package and pinout, and electrical design considerations of the MSC8113 device. MSC8113 Reference Manual (MSC8113RM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8113 device. SC140 DSP Core Reference Manual. Covers the SC3400 core architecture, control registers, clock registers, program control, and instruction set. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 42 Freescale Semiconductor Revision History 7 Revision History Table 31. Document Revision History Table 31 provides a revision history for this data sheet. Revision 0 Date Jun. 2007 * Initial public release. Description MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 43 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 010 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. FreescaleTM, the Freescale logo, CodeWarrior, and StarCore are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2008. All rights reserved. Document Number: MSC8113 Rev. 0 5/2008 |
Price & Availability of MSC8113TMP4800V
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |